This invention relates to programmable logic devices, and more particularly to programmable logic devices with increased logic and interconnection capability.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, and Cliff et al. U.S. Pat. No. 5,909,126. All of these references are hereby incorporated by reference herein in their entirety.
There is continued interest in programmable logic devices with greater logic capacity. This calls for devices with larger numbers of regions of programmable logic. It also calls for logic devices with more programmable interconnection resources for making needed connections between the increased numbers of logic regions. It is important, however, to add interconnection resources judiciously so that those resources do not begin to take up excessive amounts of space on the device, thereby unduly interfering with the amount of additional logic that can be included in the device. To accomplish this it would be desirable to find ways to organize programmable logic devices, and especially the interconnection resources in programmable logic devices, so that the efficiency of utilization of the interconnection resources can be greater. In this way more interconnectivity can be provided in the device to serve more logic in the device without simply directly scaling up the interconnection resources with the increased logic capability.
An example of a possible problem associated with merely scaling up known programmable logic device architectures is illustrated by the case of the architecture shown in above-mentioned Cliff et al. U.S. Pat. No. 5,689,195. In this type of device regions of programmable logic are disposed on the device in a plurality of rows of such regions. Each row has an associated plurality of horizontal interconnection conductors for selectively conveying signals to, from, and between the regions in that row. Region-feeding conductors are associated with each region for selectively bringing signals from the associated horizontal conductors into the region as input signals. Output signals produced by each region are selectively applied to the associated horizontal conductors. Vertical interconnection conductors are provided for selectively conveying signals between the rows of the device. Accordingly, a programmable logic device having this type of architecture basically comprises a row of logic regions and associated interconnection conductors that has been replicated a number of times and then provided with vertical interconnection conductors for interconnecting the rows. To meet the demand for larger and larger devices it may not be practical to indefinitely increase the number of regions in a row or the number of rows due to manufacturing constraints. For example, the aspect ratio of the device may tend to become too large.
In view of the foregoing, it is an object of this invention to provide improved organizations (xe2x80x9carchitecturesxe2x80x9d) for programmable logic devices.
It is a more particular object of this invention to provide programmable logic device architectures that can efficiently accommodate larger numbers of programmable logic regions.
It is another more particular object of this invention to provide programmable logic device architectures which permit higher densities of logic regions and which have more uniform horizontal and vertical characteristics so that there is less preference for one direction over the other and therefore less tendency toward designs with high aspect ratios.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices having a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region includes a plurality of regions of programmable logic and a plurality of inter-region interconnection conductors for conveying signals to and between the regions in that super-region. In some embodiments each super-region may be somewhat like a short, folded row in the exemplary devices described in the background section of this specification. For example, in these embodiments the regions in each super-region may be disposed along both sides of that super-region""s inter-region interconnection conductors. Thus in these embodiments a super-region may be viewed as a row of regions that is folded back along the associated inter-region interconnection conductors. Each region preferably includes a plurality of subregions of programmable logic. A typical subregion is programmable to perform any of several logical operations on a plurality of input signals applied to the subregion to produce an output signal of the subregion. Programmable logic connectors are associated with the regions for selectively bringing signals from the associated inter-region conductors into the region for use as inputs to the subregions in that region. Other programmable logic connectors selectively apply the subregion output signals to the associated inter-region conductors.
A plurality of horizontal inter-super-region interconnection conductors is associated with each row of super-regions for selectively conveying signals to, from, and between the super-regions in the associated row. Similarly, a plurality of vertical inter-super-region interconnection conductors is associated with each column of super-regions for selectively conveying signals to, from, and between the super-regions in the associated column. Programmable logic connectors are provided for selectively applying signals on the horizontal and vertical inter-super-region conductors to the inter-region conductors. Additional programmable logic connectors are provided for selectively applying subregion output signals to the horizontal and vertical inter-super-region conductors. And programmable logic connectors are provided for selectively interconnecting horizontal and vertical inter-super-region conductors.
The architectures of this invention can be made more uniform with respect to the horizontal and vertical axes of the device. These architectures therefore lend themselves more readily to square or nearly square layouts. This is desirable because such layouts have low aspect ratios of one or nearly one. It may also be possible to achieve greater logic densities with the architectures of this invention. The inter-super-region interconnection conductors provide a next level of routing hierarchy (beyond the routing provided at the region and super-region levels). Connectivity within the device is increased by segmenting (and thereby rendering reusable) wiring channels in aligned super-regions. Any necessary interconnections between super-regions are then made using inter-super-region conductors.
Other features that the programmable logic devices of this invention may have are the provision of two types of horizontal and/or vertical inter-super-region interconnection conductors. These are so-called xe2x80x9cglobalxe2x80x9d horizontal and/or vertical conductors that extend along the entire length of the associated row or column of super-regions, and so-called xe2x80x9chalfxe2x80x9d horizontal and/or vertical conductors that extend along one of two mutually exclusive halves of the length of the associated row or column of super-regions. The mutual exclusivities mentioned in the preceding sentence are preferred but not absolutely required.
As a possible addition or alternative to providing separate global horizontal and half horizontal conductors, two axially aligned half horizontal conductors can be programmably xe2x80x9cstitchedxe2x80x9d together to provide a global horizontal conductor when such a conductor is needed. Thus it may be possible to omit the dedicated global horizontal conductors. Or it may be preferred to have only global horizontal conductors and no half horizontal conductors. The same options exist with respect to the above-described global vertical and half vertical conductors. The design choices made with regard to the foregoing options may be influenced by the size of the device (e.g., the number of logic subregions, regions, and super-regions on the device).
If stitching of conductors is provided as mentioned in the preceding paragraph, it may be provided by programmable buffers between the conductors being stitched.
The above-mentioned programmable logic connectors for selectively bringing signals from the inter-region conductors into the region may include local conductors that are interleaved between horizontally adjacent regions. The local conductors may be of two types: (1) region-feeding conductors for bringing signals into the adjacent region or regions, and (2) local feedback conductors for making output signals of the region available as inputs to the region and possibly also horizontally adjacent regions. The region-feeding conductors are programmably connectable to the adjacent inter-region interconnection conductors in order to receive signals from the inter-region interconnection conductors.
The above-mentioned programmable logic connectors for (1) applying signals on the horizontal and vertical inter-super-region conductors to the inter-region conductors, (2) applying subregion output signals to the inter-super-region conductors, and (3) selectively interconnecting horizontal and vertical inter-super-region conductors may include drivers which are effectively shared for these various purposes. For example, one or more of these drivers may be associated with each logic subregion. Programmable logic connectors are provided for applying any of several signals to each driver. For example, these signals may include (1) one or more output signals of the associated subregion, (2) one or more global or half vertical conductor signals, and (3) one or more global or half horizontal conductor signals. The output signal of each driver may be programmably connected to (1) one or more global or half horizontal conductors, (2) one or more global or half vertical conductors, (3) one or more inter-region interconnection conductors, and (4) one or more local conductors. These drivers are therefore shared for many purposes such as (1) driving subregion output signals out onto the global and half conductors, as well as onto the inter-region interconnection conductors, (2) making connections between horizontal and vertical conductors, and (3) driving subregion output signals back onto local conductors.
Some of the programmable logic connectors feeding drivers as described in the preceding paragraph (e.g., those programmable logic connectors near the periphery of the device) may also receive signals from input/output (xe2x80x9cI/Oxe2x80x9d) pins of the device. This enables the associated drivers to also be used to drive signals from the I/O pins to the destinations mentioned above. Some I/O pins may also have dedicated drivers that programmably feed one or more global or half conductors and/or one or more inter-region interconnection conductors.
Each subregion is fed by multiple inputs. In architectures with local conductors interleaved between horizontally adjacent regions, some of these inputs come from the local conductors to the left of the region that includes that subregion, and some of these inputs come from the local conductors to the right of the region that includes that subregion.
I/O pins along the top, bottom, left, and right sides of the device may programmably select their output and/or output enable signals from one or more of the local conductors adjacent the respective top, bottom, left, or right side of the device.
From the foregoing it will be apparent that the region-feeding local conductors are preferably not directly connected to the global or half conductors. In order to reach a local line, these global or half conductor signals must first be routed through the above-mentioned drivers and also in most cases through inter-region interconnection conductors. This interconnection architecture reduces the number of programmable connections used to connect signals to the local lines.
Some devices may not have dedicated local feedback lines. This saves programmable interconnect which is wasted if the local feedback lines are not used. For these devices, the functionality of the local feedback lines can be achieved by routing signals to the region-feeding conductors (e.g., via the inter-region interconnection conductors). If this is done, it may be advantageous to make some of the inter-region interconnection conductors span only a very small number of the logic regions, while other inter-region interconnection conductors span larger numbers of the logic regions.
From the foregoing it will be seen that the interconnection resource architectures of this invention are hierarchical to an increased degree (e.g., from global or half global to inter-region to local). Such architectures help to reduce the area required for a programmable logic device with a given amount of logic capability by decreasing the total number of programmable interconnections required. Such architectures also help to increase the speed of the device by reducing the parasitic loading due to excessive numbers of programmable interconnections.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.